With the prosperous growth of electrical products consumption, the current trend of consumers' demand, including increased portability, computing power, memory capacity and energy efficiency, is for the dimension of such products to almost always be toward small size and delicacy design.
The continual reduction in feature sizes results in greater demands on the techniques used to form the critical features in the integrated circuits. For example, lithography is commonly used to pattern these features. Because lithography is typically accomplished by projecting light or radiation onto a surface, the ultimate resolution of a particular lithographic technique depends upon factors such as optics and light or radiation wavelength.
In many applications it is advantageous to have features such as lines and spaces to be as small as possible. Smaller line widths or periods translate into higher performance and/or higher density circuits. Hence, the microelectronics industry is on a continual quest to reduce the minimum resolution in photolithography systems and thereby reduce the line widths or periods on patterned substrates.
There exists a need for a method of fabricating sub-lithographic sized line and space patterns that utilizes conventional lithography systems to fabricate the sub-lithographic sized line and space patterns with a feature size that is less than the lithography limit of the lithography system.